1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices with a memory block mounted thereon together with a logic circuit and thus used.
2. Description of the Background Art
There is a system LSI developed with a large-capacity dynamic random access memory (DRAM) and a large-scale logic circuit mounted thereon in a mixed manner. Such a system LSI has been materialized attributed to the recent advance of semiconductor microprocessing technology. It can incorporate a DRAM therein and have a memory bus width in a chip thereof that is extended without any limitation imposed thereon by an external terminal. For example, a bus width extended from 16 bits, as conventional, to multiple bits of 128-256 bits allows data to be rapidly transferred and digital devices to provide high performance and operate with reduced power consumption.
Such a system LSI as described above is often produced as an application-specific IC (ASIC). For the ASIC, a DRAM incorporated therein is required to have a core having a different memory capacity depending on the application.
FIG. 12 illustrates an arrangement of a circuit block having arranged therein a conventional DRAM core's memory cell array and sense amplifier.
As shown in FIG. 12, on opposite sides of a memory cell array MA#2 there are provided sense amplifier bands SAB#2 and SAB#3. On a side of sense amplifier band SAB#2, memory cell array MA#2 and sense amplifier band SAB#3 there are provided a column select control circuit 502, a row select control circuit 504, and a column select control circuit 506, respectively. Sense amplifier band SAB#2, memory cell array MA#2 and sense amplifier band SAB#3 are adjacent to square regions, respectively, which will be referred to as a center cross circuit band CCCB#2, a center circuit band CCB#2 and a center cross circuit band CCCB#3,respectively. As such, column select control circuit 502, row select control circuit 504 and column select control circuit 506 exist internal to center cross circuit band CCCB#2, center circuit band CCB#2 and center cross circuit band CCCB#3, respectively.
FIG. 13 is a block diagram for illustrating a signal input to the FIG. 12 center cross circuit band CCCB#2.
With reference to FIG. 13, center circuit band CCB#1 includes a row predecode circuit 514, an address latch circuit 512, a row decoder 516 and a sense amplifier control circuit 518.
Center circuit band CCB#2 includes a row predecode circuit 524, an address latch circuit 522, a row decoder 526 and a sense amplifier control circuit 528. Row predecode circuit 524, address latch circuit 522, row decoder 526 and sense amplifier control circuit 528 correspond to the FIG. 12 row select control circuit 504.
Center cross circuit band CCCB#2 is provided with a row decode circuit 520. Row decode circuit 520 corresponds to the FIG. 12 column select control circuit 502.
Row decoders 516 and 526 output to their respective adjacent memory cell arrays a signal MWLD&lt;m:0&gt; driving a main word line to select a memory cell row. In response to signal MWLD&lt;m:0&gt;, a memory cell array has a word line activated.
In response to a memory cell row having been selected, sense amplifier control circuit 528 connects a sense amplifier to a bit line and activates the sense amplifier. As such, conventionally, together with row predecode circuit 524 and row decoder 526 which are common in providing a row address processing, sense amplifier control circuit 528 is arranged as the FIG. 12 row select control circuit 504 in center circuit band CCB#2 corresponding to a region adjacent to a memory cell array.
As such, sense amplifier control circuit 528 outputs a bit line equalization signal and a bit line isolation signal to both of sense amplifier band SAB#2 arranged between memory cell arrays MA#2 and MA#1 and a sense amplifier band SAB#3 (not shown). Furthermore, sense amplifier control circuit 528 outputs a sense amplifier activation signal SE, /SE to sense amplifier band SAB#2.
FIG. 14 is a circuit diagram showing a configuration of the FIG. 13 address latch circuit 522.
As shown in FIG. 14, address latch circuit 522 includes a latch circuit 532 latching a signal XBLK&lt;n&gt; in synchronization with a signal XLAT&lt;bankn&gt;, a latch circuit 534 latching a signal XBLK&lt;n-1&gt; in synchronization with signal XLAT&lt;bankn&gt;, and a latch circuit 536 latching a row address signal RA&lt;k:0&gt; in synchronization with signal XLAT&lt;bankn&gt;.
Latch circuit 532 outputs a signal XBLATL indicating that when memory cell array #n is selected, sense amplifier bands SAB#n and SAB#n+1 are connected to memory cell array #n to use a sense amplifier.
Latch circuit 534 outputs a signal XBLATR for activating a sense amplifier of sense amplifier band SAB#n when memory cell array #n-1 is selected.
Furthermore, latch circuit 536 holds and outputs a row address signal RALAT&lt;k:0&gt; input in response to a memory block having been selected. Row address signal RALAT&lt;k:0&gt; is input to and predecoded in the FIG. 13 row predecode circuit 524. The predecoded signal is fed to row decoder 136 to activate any one of signal MWLD&lt;m:0&gt; for driving a word line. Note that signal XBLK&lt;n&gt; corresponds to signal XBLK&lt;2&gt;.
Address latch circuit 512 is similar in configuration to the FIG. 14 address latch circuit 522 and a description thereof will thus not be repeated, although for address latch circuit 512, signal XBLK&lt;n&gt; corresponds to signal XBLK&lt;1&gt;.
FIG. 15 is a circuit diagram showing a configuration of the FIG. 13 row decode circuit 520.
As shown in FIG. 15, row decode circuit 138 includes an AND circuit 542 receiving a bank select signal YBANK&lt;n&gt; and a signal XBLATL output from address latch circuit 522, an AND circuit 544 receiving a bank select signal YBANK&lt;n&gt; and a signal XBLATR output from address latch circuit 522, an NOR circuit 546 receiving a signal output from AND circuit 542 and that output from AND circuit 544, an inverter 548 receiving and inverting a signal output from NOR circuit 546, an NAND circuit 556 receiving a column select signal CSLR&lt;i:0&gt; for read operation and a signal output from inverter 548, an inverter 558 receiving and inverting a signal output from NAND circuit 556, and an inverter 560 receiving and inverting a signal output from inverter 558 and outputting a signal CSLRD&lt;i:0&gt; driving a column select line.
Row decode circuit 520 also includes an NAND circuit 550 receiving a column select signal CSLW&lt;i:0&gt; for write operation and a signal output form inverter 548, an inverter 552 receiving and inverting a signal output form NAND circuit 550, and an inverter 554 receiving and inverting a signal output form inverter 552 and outputting a signal CSLWD&lt;i:0&gt; driving a column select line.
FIG. 16 is a circuit diagram showing a configuration of the FIG. 13 sense amplifier control circuit 528.
As shown in FIG. 16, sense amplifier control circuit 528 includes a level conversion circuit 572 receiving and inverting signal XBLATL for level conversion, a buffer circuit 574 receiving a signal output from level conversion circuit 572 and outputting a bit line equalization signal BLEQR#3, a level conversion circuit 576 receiving and converting signal XBLATL in level, and a buffer circuit 578 receiving a signal output from level conversion circuit 576 and outputting a bit line isolation signal BLIL#3. Although not shown, bit line equalization signal BLEQE#3 and bit line isolation signal BLIL#3 are transmitted to sense amplifier band SAB#3 arranged between memory cell arrays MA#2 and MA#3.
Sense amplifier control circuit 528 also includes a level conversion circuit 596 receiving and inverting signal XBLATL for level conversion, a buffer circuit 598 receiving a signal output from level conversion circuit 596 and outputting a bit line equalization signal BLEQL#2, a level conversion circuit 600 receiving and converting signal XBLATL in level, and a buffer circuit 602 receiving a signal output from level conversion circuit 600 and outputting a bit line isolation signal BLIR#2.
Sense amplifier control circuit 528 also includes an NOR circuit 580 receiving signals XBLATR and XBLATL, an inverter 582 receiving and inverting a signal output from NOR circuit 580, an NAND circuit 584 receiving a signal output from inverter 582 and a signal XSE indicative of a timing at which a sense amplifier is activated, an inverter 586 receiving and inverting a signal output from NAND circuit 584, a level conversion circuit 588 converting in level a signal output from inverter 586, a buffer circuit 590 receiving a signal output from level conversion circuit 588 and outputting a sense amplifier activation signal SE#2, a level conversion circuit 592 receiving and converting in level a signal output from NAND circuit 584, and a buffer circuit 594 receiving a signal output from level conversion circuit 592 and outputting a sense amplifier activation signal /SE#2.
Although not shown, bit line equalization signal BLEQR#2, bit line isolation signal BLIL#2 and sense amplifier activation signals SE#2 and /SE#2 are transmitted to sense amplifier band SAB#2 arranged between memory cell arrays MA#1 and MA#2.
Conventionally, such a DRAM core as described above has a memory capacity changed by increasing/decreasing the number of memory cell arrays MA#n, wherein n represents a natural number.
Referring again to FIG. 13, conventionally a circuit responsible for selecting a column is arranged in center cross circuit band CCCB#2 and that responsible for selecting a row is arranged in center circuit bands CCB#1, CCB#2. Thus, sense amplifier band SAB#2 receives bit line equalization signal BLEQR#2, bit line isolation signal BLIL#2 and sense amplifier activation signals SE, /SE from sense amplifier control circuit 528 arranged in center circuit band CCB#2. Furthermore, bit line equalization signal BLEQL#2 and bit line isolation signal BLIR#2 are output from sense amplifier control circuit 518 arranged in center circuit band CCB#1, and input to sense amplifier band SAB#2.
As such, as shown in FIG. 12, center cross circuit band CCCB#2 is heavily populated with signal lines. Since center circuit band CCB#2 and center cross circuit band CCCB#2 communicate a large number of signals therebetween, changing the number of memory cell arrays requires an effort in modifying the layout data indicative of an arrangement of circuits, interconnections and the like in designing the same, to change the memory capacity of interest.